3 ms·

Can you expand on this? Why can't 5nm chips handle higher voltages?

• hristov 5y ago
  If your channel is very very thin, a sufficiently high voltage will cause conduction over it, even when it is not supposed to be conductive.
  • runnerup 5y ago
    If you can make a "5nm" channel...why can't the machine just make the channel wider? Like I can use a 1/8" router bit to make a 1/8" wide channel, or I can use that same router bit to make a 1" wide channel. I know these machines don't use routers but I don't really understand why they can't create larger features if they can create smaller ones. I suspect they can.... but maybe its just not cost-effective. Why use a 5nm process to create a 180nm feature-size chip, when you can use a 180nm process for 99% less cost. If I'm wrong please correct my misconception!
    • marcan_42 5y ago
      It's not width, it's depth. Things like gate oxide are deposited as a layer through a chemical process. That layer is the same thickness across the entire chip, and it scales down with the node. Gate oxide thickness determines your maximum gate voltage. Chips aren't 2D structures, they're built out of 3D layers and all those layers have a constant thickness.
      • runnerup 5y ago
        Thanks marcan :) and thanks for all your work towards bringing linux to M1.