5 ms·

Many 20+ year old fabs are still expanding and the old machines are very hard to come by. We have recently even started converting 300mm machines to run 200mm

Many 20+ year old fabs are still expanding and the old machines are very hard to come by. We have recently even started converting 300mm machines to run 200mm wafers because those machines are easier to find. Not every chip runs on the latest and greatest technology. For instance there is no need for a 5nm power management chip...180nm is perfectly capable of handling it efficiently.

xxpor 5y ago
I assume this is a non starter since no one (that I know of) is doing it, but is there a reason you can't "just" apply a 200mm mask on top of a 300mm wafer? If the limitation is the 300mm wafer costs more and makes the chips too expensive, how much would the cost have to increase in order to make it worth it? ((300mm^2pi) - (200mm^2pi))/(300mm^2*pi) % roughly?
- haneefmubarak 5y ago
  The kind of precision and accuracy tolerances you need in these machines basically make it so that everything has to be exactly right. The 200mm mask won't have a place to "fit correctly" in the 300mm machine and so you won't be able to get the precision and accuracy you need. Remember: a silicon chip is actually made of many layers, which means many masks (1 mask per layer). Additionally, the method by which 200mm masks and 300mm masks are actually used in the etching process can vary significantly because of physics that I honestly don't have a phenomenal insight into. Making larger wafers drives prices up, because the process of making a monocrystal larger and larger, but I don't think that's a major cost factor except for super cheap chips. The minimum cost of a 200mm wafer is about $2/in^2 and the minimum cost for a 300mm wafer is about $3/in^2, in case that's helpful.
  - mjevans 5y ago
    The pad size for external wires might dominate the design for extremely simple designs, however couldn't a combination of these factors help? * Shrink the average node size 1-2 times (E.G. 180nm to 90 or 45nm) * Combine popular combinations of products into a single package that can have interlinks cut by laser or skipped at the metal traces stage? * Generally consolidate similar products within fewer variations? The slightly greater cost of the physical wafer is supposed to be offset by the increased machine throughput and the die shrinks possible, as well as ideally fewer defects by using newer processes. An extremely inexpensive set of processes for 300mm wafers would also be a good target for long term bulk semiconductor production.
- makomk 5y ago
  I assume there's other equipment still in use on the line that can only handle 200mm wafers, otherwise it'd make sense to upgrade to 300mm and take the extra capacity increase - the masks are stepped across the wafers anyway, there's no reason in principle they can't just add more chips to fill in the extra area if they have the ability to process 300mm wafers.
- brennanpeterson 5y ago
  Masks are not whole wafer , except in some packaging cases. The mask illuminates a 25*35 area, for both 300mm and 200mm. Masks are not a significant expense for most processes. Nor is the bare wafer. It is all the process steps that drive the cost. 300mm qafer
dehrmann 5y ago
I'm sure the answer is "it depends," but when do parts get so small that you stop getting higher part yield per wafer because the component just gets too small? Are there reliability or ruggedness concerns where some use cases prefer older processes?
- deleted 5y ago
  [deleted]
cnasc 5y ago
> For instance there is no need for a 5nm power management chip But like what if you did it anyway? I remember pondering this while looking at some guitar pedal schematics. A lot of them use ICs that are basically ancient. Do newer processes have anything to offer (even if it wouldn’t be cost-efficient)?
- bserge 5y ago
  Cost efficiency is the key, though. It'd be kind of like newer 2.5" SSDs, the actual drive takes up a fraction of the space inside. Just without the benefit of being cheaper. Power savings would pale in comparison to cost and for many components like amps, bigger = more power.
- lmilcin 5y ago
  For these kinds of chips there is usually nothing the new process can offer other than higher development costs, higher production costs, longer cycle times, lower yields, higher noise levels and higher EMC susceptibility. A chip that fits its package comfortably at 180nm will not benefit from converting it 5nm process at all. The main reasons to get with a smaller process node is to put more transistor on the same area, use less power or reduce the size of the chip, that's it. A power management chip does not qualify. There is one more reason: if you are already invested in smaller process node or when it is difficult to find machinery for older process.
  - deleted 5y ago
    [deleted]
- bsder 5y ago
  No. Especially not for something like guitar pedals. First, you are very likely "pad limited", the pads to connect the chip to the package are much larger than the actual active chip area. Second, newer processes are rarely better at analog-type things. Leakage is worse, noise is worse, etc. Generally, you have to add to the transistor "length" (minimum dimension) in order to get back analog performance parameters. Third, newer processes have to run at really small power supply voltages. Old-school metal gate CMOS in 0.5um or larger was good to 18V+--really good for things like guitar pedals. If you have the tools, you'd be better off doing a guitar pedal in a very old technology.
userbinator 5y ago
If you look at the lists provided by IC prototyping services, you'll see that 0.7u (700nm) is still available from ON Semi: https://europractice-ic.com/wp-content/uploads/2020/11/General-MPW-EUROPRACTICE-201116-v18.pdf https://europractice-ic.com/wp-content/uploads/2020/11/Gener... ...and also happens to be one of the cheapest, at 300 euros/mm^2. This was the highest-density process in the early 90s and used for CPUs such as the 486 and Pentium.
- adgjlsfhk1 5y ago
  price per area isn't am especially useful metric since a smaller node gets more transistors per area for most applications.
7373737373 5y ago
Is there any chance such machines will be available to hobbyists some day? The only person I've ever seen attempt something like this is Sam Zeloof: https://www.youtube.com/watch?v=XrEC2LGGXn0 https://www.youtube.com/watch?v=XrEC2LGGXn0 I'm wondering if we'll get to the point where a single person can manufacture a chip.
- Const-me 5y ago
  I wouldn't want any of that stuff at my home: https://www.bloomberg.com/news/features/2017-06-15/american-chipmakers-had-a-toxic-problem-so-they-outsourced-it https://www.bloomberg.com/news/features/2017-06-15/american-...
- showerst 5y ago
  FYI you might like this series from Huygens optics, although his more targeted at microscale lenses than transistors. https://youtu.be/_w0Z2Y5vaAQ https://youtu.be/_w0Z2Y5vaAQ
marcan_42 5y ago
Not only that; you can't do 5nm power management chips. At 5nm the highest voltage you can handle on your I/O is 1.2V or perhaps 1.8V. You can't even make USB transceivers on that process, which is why the Apple Silicon macs use external USB level translation chips!
- gautamcgoel 5y ago
  Can you expand on this? Why can't 5nm chips handle higher voltages?
  - hristov 5y ago
    If your channel is very very thin, a sufficiently high voltage will cause conduction over it, even when it is not supposed to be conductive.
    - runnerup 5y ago
      If you can make a "5nm" channel...why can't the machine just make the channel wider? Like I can use a 1/8" router bit to make a 1/8" wide channel, or I can use that same router bit to make a 1" wide channel. I know these machines don't use routers but I don't really understand why they can't create larger features if they can create smaller ones. I suspect they can.... but maybe its just not cost-effective. Why use a 5nm process to create a 180nm feature-size chip, when you can use a 180nm process for 99% less cost. If I'm wrong please correct my misconception!
      - marcan_42 5y ago
        It's not width, it's depth. Things like gate oxide are deposited as a layer through a chemical process. That layer is the same thickness across the entire chip, and it scales down with the node. Gate oxide thickness determines your maximum gate voltage. Chips aren't 2D structures, they're built out of 3D layers and all those layers have a constant thickness.
        5y ago

xxpor 5y ago

I assume this is a non starter since no one (that I know of) is doing it, but is there a reason you can't "just" apply a 200mm mask on top of a 300mm wafer? If the limitation is the 300mm wafer costs more and makes the chips too expensive, how much would the cost have to increase in order to make it worth it? ((300mm^2pi) - (200mm^2pi))/(300mm^2*pi) % roughly?

haneefmubarak 5y ago
The kind of precision and accuracy tolerances you need in these machines basically make it so that everything has to be exactly right. The 200mm mask won't have a place to "fit correctly" in the 300mm machine and so you won't be able to get the precision and accuracy you need. Remember: a silicon chip is actually made of many layers, which means many masks (1 mask per layer). Additionally, the method by which 200mm masks and 300mm masks are actually used in the etching process can vary significantly because of physics that I honestly don't have a phenomenal insight into. Making larger wafers drives prices up, because the process of making a monocrystal larger and larger, but I don't think that's a major cost factor except for super cheap chips. The minimum cost of a 200mm wafer is about $2/in^2 and the minimum cost for a 300mm wafer is about $3/in^2, in case that's helpful.
- mjevans 5y ago
  The pad size for external wires might dominate the design for extremely simple designs, however couldn't a combination of these factors help? * Shrink the average node size 1-2 times (E.G. 180nm to 90 or 45nm) * Combine popular combinations of products into a single package that can have interlinks cut by laser or skipped at the metal traces stage? * Generally consolidate similar products within fewer variations? The slightly greater cost of the physical wafer is supposed to be offset by the increased machine throughput and the die shrinks possible, as well as ideally fewer defects by using newer processes. An extremely inexpensive set of processes for 300mm wafers would also be a good target for long term bulk semiconductor production.
makomk 5y ago
I assume there's other equipment still in use on the line that can only handle 200mm wafers, otherwise it'd make sense to upgrade to 300mm and take the extra capacity increase - the masks are stepped across the wafers anyway, there's no reason in principle they can't just add more chips to fill in the extra area if they have the ability to process 300mm wafers.
brennanpeterson 5y ago
Masks are not whole wafer , except in some packaging cases. The mask illuminates a 25*35 area, for both 300mm and 200mm. Masks are not a significant expense for most processes. Nor is the bare wafer. It is all the process steps that drive the cost. 300mm qafer

dehrmann 5y ago

I'm sure the answer is "it depends," but when do parts get so small that you stop getting higher part yield per wafer because the component just gets too small? Are there reliability or ruggedness concerns where some use cases prefer older processes?

deleted 5y ago
[deleted]

cnasc 5y ago

> For instance there is no need for a 5nm power management chip But like what if you did it anyway? I remember pondering this while looking at some guitar pedal schematics. A lot of them use ICs that are basically ancient. Do newer processes have anything to offer (even if it wouldn’t be cost-efficient)?

bserge 5y ago
Cost efficiency is the key, though. It'd be kind of like newer 2.5" SSDs, the actual drive takes up a fraction of the space inside. Just without the benefit of being cheaper. Power savings would pale in comparison to cost and for many components like amps, bigger = more power.
lmilcin 5y ago
For these kinds of chips there is usually nothing the new process can offer other than higher development costs, higher production costs, longer cycle times, lower yields, higher noise levels and higher EMC susceptibility. A chip that fits its package comfortably at 180nm will not benefit from converting it 5nm process at all. The main reasons to get with a smaller process node is to put more transistor on the same area, use less power or reduce the size of the chip, that's it. A power management chip does not qualify. There is one more reason: if you are already invested in smaller process node or when it is difficult to find machinery for older process.
- deleted 5y ago
  [deleted]
bsder 5y ago
No. Especially not for something like guitar pedals. First, you are very likely "pad limited", the pads to connect the chip to the package are much larger than the actual active chip area. Second, newer processes are rarely better at analog-type things. Leakage is worse, noise is worse, etc. Generally, you have to add to the transistor "length" (minimum dimension) in order to get back analog performance parameters. Third, newer processes have to run at really small power supply voltages. Old-school metal gate CMOS in 0.5um or larger was good to 18V+--really good for things like guitar pedals. If you have the tools, you'd be better off doing a guitar pedal in a very old technology.

userbinator 5y ago

If you look at the lists provided by IC prototyping services, you'll see that 0.7u (700nm) is still available from ON Semi: https://europractice-ic.com/wp-content/uploads/2020/11/General-MPW-EUROPRACTICE-201116-v18.pdf https://europractice-ic.com/wp-content/uploads/2020/11/Gener... ...and also happens to be one of the cheapest, at 300 euros/mm^2. This was the highest-density process in the early 90s and used for CPUs such as the 486 and Pentium.

adgjlsfhk1 5y ago
price per area isn't am especially useful metric since a smaller node gets more transistors per area for most applications.

7373737373 5y ago

Is there any chance such machines will be available to hobbyists some day? The only person I've ever seen attempt something like this is Sam Zeloof: https://www.youtube.com/watch?v=XrEC2LGGXn0 https://www.youtube.com/watch?v=XrEC2LGGXn0 I'm wondering if we'll get to the point where a single person can manufacture a chip.

Const-me 5y ago
I wouldn't want any of that stuff at my home: https://www.bloomberg.com/news/features/2017-06-15/american-chipmakers-had-a-toxic-problem-so-they-outsourced-it https://www.bloomberg.com/news/features/2017-06-15/american-...
showerst 5y ago
FYI you might like this series from Huygens optics, although his more targeted at microscale lenses than transistors. https://youtu.be/_w0Z2Y5vaAQ https://youtu.be/_w0Z2Y5vaAQ

marcan_42 5y ago

Not only that; you can't do 5nm power management chips. At 5nm the highest voltage you can handle on your I/O is 1.2V or perhaps 1.8V. You can't even make USB transceivers on that process, which is why the Apple Silicon macs use external USB level translation chips!

gautamcgoel 5y ago
Can you expand on this? Why can't 5nm chips handle higher voltages?
- hristov 5y ago
  If your channel is very very thin, a sufficiently high voltage will cause conduction over it, even when it is not supposed to be conductive.
  - runnerup 5y ago
    If you can make a "5nm" channel...why can't the machine just make the channel wider? Like I can use a 1/8" router bit to make a 1/8" wide channel, or I can use that same router bit to make a 1" wide channel. I know these machines don't use routers but I don't really understand why they can't create larger features if they can create smaller ones. I suspect they can.... but maybe its just not cost-effective. Why use a 5nm process to create a 180nm feature-size chip, when you can use a 180nm process for 99% less cost. If I'm wrong please correct my misconception!
    - marcan_42 5y ago
      It's not width, it's depth. Things like gate oxide are deposited as a layer through a chemical process. That layer is the same thickness across the entire chip, and it scales down with the node. Gate oxide thickness determines your maximum gate voltage. Chips aren't 2D structures, they're built out of 3D layers and all those layers have a constant thickness.
      - 5y ago