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Interesting idea about the power usage of the interconnect. I don't remember this being discussed as an issue in tech press writings about multisocket Xeon or E
by fulafel 5y ago
Interesting idea about the power usage of the interconnect. I don't remember this being discussed as an issue in tech press writings about multisocket Xeon or EPYC systems. Do you happen to have any references?
- mlyle 5y agohttps://images.anandtech.com/doci/13124/IF%20Power%20EPYC.png https://images.anandtech.com/doci/13124/IF%20Power%20EPYC.pn... Here's EPYC 7601's "IF" power (it's really all the uncore power) vs. the core power. Going outside the chip means swinging lots of capacitance up and down, and modern interconnects swing that capacitance fast.
- sroussey 5y agoAlso why pci 4 and 5 require much more cooling for more than the cpu.
- kllrnohj 5y agoAnd that's only for a 2p setup. An 8p setup would need even more interconnects per CPU depending on the architecture (eg, ring, mesh, etc..), which would have further impacts to performance depending on which tradeoffs are made.