Some cores are open source and you can see for yourself. Rename logic from BOOM, a RISC-V core written in a DSL embedded in Scala: https://github.com/riscv-bo

Some cores are open source and you can see for yourself. Rename logic from BOOM, a RISC-V core written in a DSL embedded in Scala: https://github.com/riscv-boom/riscv-boom/blob/1ef2bc6f6c98e5b0b1fd77899f5ff48280c75f51/src/main/scala/exu/rename/rename-stage.scala https://github.com/riscv-boom/riscv-boom/blob/1ef2bc6f6c98e5... From RSD, a core designed for FPGAs written in SystemVerilog: https://github.com/rsd-devel/rsd/blob/master/Processor/Src/RenameLogic/ https://github.com/rsd-devel/rsd/blob/master/Processor/Src/R... And then there's Alibaba's recently open-sourced XuanTie C910, which contains this Verilog… which is completely unreadable. Seems like it was produced by some kind of code generator that they didn't open-source? https://github.com/T-head-Semi/openc910/blob/d4a3b947ec9bb8fa72327f1ef87f659c252246a4/C910_RTL_FACTORY/gen_rtl/rtu/rtl/ct_rtu_pst_vreg.v https://github.com/T-head-Semi/openc910/blob/d4a3b947ec9bb8f...