"x86 has an innate disadvantage [...] fattening up the frontend" this is inherent largely because of ISA complexity and variable width instructions? "M1 core w

"x86 has an innate disadvantage [...] fattening up the frontend" this is inherent largely because of ISA complexity and variable width instructions? "M1 core which is [...] much wider than both AMD and Intel" The core width you're referring to is the decoder width yeah? As another poster pointed out the M1 has a large reorder buffer as well. Combined with the ability to index a larger L1 cache what I'm getting here is that the M1 can be a lot better about scheduling instructions (and perhaps even running non-interfering instructions in parallel on a given core (is that a thing?)) because the frontend has more power and space to do so. I guess that efficiency is then a big part of the puzzle on why the increased bandwidth to ram makes such an impact?