5 ms·

I wonder how things like register renaming (or pipelining) are implemented. It would seem difficult even in a high level language, but they do it inside the pro

I wonder how things like register renaming (or pipelining) are implemented. It would seem difficult even in a high level language, but they do it inside the processor. Is this in microcode that runs on the "actual" processor? Or is it in hardware? Do they write th algorithm in a language like VHDL or Verilog?

brucedawson 5y ago
Register renaming is implemented in hardware. Because it is used on every instruction it is on the critical path and is probably hand-optimized. Here is some more reading on this topic: https://en.wikipedia.org/wiki/Register_renaming https://en.wikipedia.org/wiki/Register_renaming
dnautics 5y ago
All of the above, I believe.
monocasa 5y ago
Renaming isn't really done in microcode. Microcode is just another source for ops that get renamed. All of the renaming happens in hardware, and boils down to a handful of tables inside the processor.
comex 5y ago
Some cores are open source and you can see for yourself. Rename logic from BOOM, a RISC-V core written in a DSL embedded in Scala: https://github.com/riscv-boom/riscv-boom/blob/1ef2bc6f6c98e5b0b1fd77899f5ff48280c75f51/src/main/scala/exu/rename/rename-stage.scala https://github.com/riscv-boom/riscv-boom/blob/1ef2bc6f6c98e5... From RSD, a core designed for FPGAs written in SystemVerilog: https://github.com/rsd-devel/rsd/blob/master/Processor/Src/RenameLogic/ https://github.com/rsd-devel/rsd/blob/master/Processor/Src/R... And then there's Alibaba's recently open-sourced XuanTie C910, which contains this Verilog… which is completely unreadable. Seems like it was produced by some kind of code generator that they didn't open-source? https://github.com/T-head-Semi/openc910/blob/d4a3b947ec9bb8fa72327f1ef87f659c252246a4/C910_RTL_FACTORY/gen_rtl/rtu/rtl/ct_rtu_pst_vreg.v https://github.com/T-head-Semi/openc910/blob/d4a3b947ec9bb8f...

brucedawson 5y ago

Register renaming is implemented in hardware. Because it is used on every instruction it is on the critical path and is probably hand-optimized. Here is some more reading on this topic: https://en.wikipedia.org/wiki/Register_renaming https://en.wikipedia.org/wiki/Register_renaming

dnautics 5y ago

All of the above, I believe.

monocasa 5y ago

Renaming isn't really done in microcode. Microcode is just another source for ops that get renamed. All of the renaming happens in hardware, and boils down to a handful of tables inside the processor.

comex 5y ago

Some cores are open source and you can see for yourself. Rename logic from BOOM, a RISC-V core written in a DSL embedded in Scala: https://github.com/riscv-boom/riscv-boom/blob/1ef2bc6f6c98e5b0b1fd77899f5ff48280c75f51/src/main/scala/exu/rename/rename-stage.scala https://github.com/riscv-boom/riscv-boom/blob/1ef2bc6f6c98e5... From RSD, a core designed for FPGAs written in SystemVerilog: https://github.com/rsd-devel/rsd/blob/master/Processor/Src/RenameLogic/ https://github.com/rsd-devel/rsd/blob/master/Processor/Src/R... And then there's Alibaba's recently open-sourced XuanTie C910, which contains this Verilog… which is completely unreadable. Seems like it was produced by some kind of code generator that they didn't open-source? https://github.com/T-head-Semi/openc910/blob/d4a3b947ec9bb8fa72327f1ef87f659c252246a4/C910_RTL_FACTORY/gen_rtl/rtu/rtl/ct_rtu_pst_vreg.v https://github.com/T-head-Semi/openc910/blob/d4a3b947ec9bb8f...