3 ms·
> 1: add eax, 1 > 2: mov ebx, eax > 3: xor eax, eax > 4: add eax, ecx > Ideally we would like our awesome out-of-order processor to execute instructions 1 a
by commandlinefan 5y ago
> 1: add eax, 1
> 2: mov ebx, eax
> 3: xor eax, eax
> 4: add eax, ecx
> Ideally we would like our awesome out-of-order processor to execute instructions 1 and 3 in parallel. There is a literal data dependency between them, but a sufficiently advanced processor could detect that this dependency is artificial.
This doesn't seem right... instruction 2 does need to run after instruction 1 and before instruction 3.
- monocasa 5y agoNot if it's renamed. Instruction 2 does need to run after instruction 1, but instruction 3 doesn't need to run after them. xor eax, eax doesn't depend on the previous value of eax (because xoring anything at all with itself is zero), so you can assign it a new physical register file slot and just set it to zero.
- brucedawson 5y agoYep, exactly. The rule of thumb is that whenever a register is written to a new register mapping is created. For instruction #1 eax might be assigned to physical register 103. It maintains that identity for instruction #2. For instruction #3 eax can be assigned to, let's say, physical register 67. Then for instruction #4 it could be assigned physical register 92. The only tricky thing is that instruction #3 also reads from eax, which normally would cause a dependency, but because XOR doesn't depend on the register contents this clever optimization applies. Here's another variant: > 1: add eax, 1 > 2: mov ebx, eax > 3: mov eax, 42 > 4: add eax, ecx Here instruction 3 writes the constant 42 to the register. This might make it clearer why instruction #3 can run in parallel with or before instruction #1. Note that the results must be _retired_ in order, but execution can happen out of order.