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You're right: "In order to get to this point, Intel had to cut down some of the features of its P-core, and improve some features on the E-core. The biggest th
by 37ef_ced3 5y ago
You're right:
"In order to get to this point, Intel had to cut down some of the features of its P-core, and improve some features on the E-core. The biggest thing that gets the cut is that Intel is losing AVX-512 support inside Alder Lake. When we say losing support, we mean that the AVX-512 is going to be physically fused off, so even if you ran the processor with the E-cores disabled at boot time, AVX-512 is still disabled."
"But it does mean that AVX-512 is probably dead for consumers."
"Intel isn’t even supporting AVX-512 with a dual-issue AVX2 mode over multiple operations - it simply won’t work on Alder Lake. If AMD’s Zen 4 processors plan to support some form of AVX-512 as has been theorized, even as dual-issue AVX2 operations, we might be in some dystopian processor environment where AMD is the only consumer processor on the market to support AVX-512."
https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures/5 https://www.anandtech.com/show/16881/a-deep-dive-into-intels...
It's shocking how Intel has failed with AVX-512, and unfortunate for those who embraced the technology.
- neogodless 5y agoIt's odd, because in today's review, they have this to say: > I have to say a side word about AVX-512 support, because we found it. If you’re prepared to disable the E-cores, and use specific motherboards, it works. After Intel spent time saying it was fused off, we dug into the story and found it still works for those that need it. It’s going to be interesting to hear how this feature will be discussed by Intel in future. There's a whole page on it: https://www.anandtech.com/show/17047/the-intel-12th-gen-core-i912900k-review-hybrid-performance-brings-hybrid-complexity/2 https://www.anandtech.com/show/17047/the-intel-12th-gen-core...
- klelatti 5y agoThis is incredibly bizarre especially given AVX-512 takes quite a lot of transistors. A late design decision to try to limit power use?
- monocasa 5y agoIt's to allow easy e-core p-core thread migrations in the OS. They probably weren't intending the p-cores to be matched with e-cores when the RTL was being initially written for the p-cores, which would have been a few years ago.
- klelatti 5y agoVery good point. I guess they both cores have to have identical ISAs as they don’t know which instructions will be needed at the point at which they’re deciding which core to use.
- selectodude 5y agoOne thing that I genuinely appreciate about AMD is that I don't need to do any research to see what CPUs support what. They have a handful of SKUs, they're all straightforward, you spend what you're willing to and go from there. I feel like Intel requires me to do a bunch of research to see if the CPU I've picked checks all the boxes. Then I buy my AMD and deal with their weird driver issues and throw my hands up.
- ksec 5y ago>I feel like Intel requires me to do a bunch of research to see if the CPU I've picked checks all the boxes. I will not be surprised if Intel follows the AMD example soon. Pat Gelsinger is a product person. And generally Product person understand these issues better. Compared to Marketing / Financial people who have zero understanding. ( I dont want to bash them too much but seriously I have never met a marketing / financial guy who is any good at products in the 20+ years. )
- stagger87 5y agoWow, and 2 FMA units/ports as well? Gotta love that the first consumer chip with 2 x AVX-512 FMA units doesn't officially support it.
- ksec 5y agoMy suspicious / theory is that Intel needed the hybrid design for Mobile, otherwise there is no way to keep up with AMD in terms of pref / watt. So they basically throw this hybrid design on desktop as test bed before launching it on Mobile.
- dralley 5y agoIt's probably part of their fab strategy. They want to offer x86 IP blocks to SoC customers, and it's nice to have options tuned for performance and ones tuned for size / efficiency.