IIRC, hypervisors have to preserve CPU registers and other processor-related state when switching between "worlds". This is why mitigations for CPU vulnerabilit

IIRC, hypervisors have to preserve CPU registers and other processor-related state when switching between "worlds". This is why mitigations for CPU vulnerabilities affects hypervisors too. Most compilers assume that emitting the code in certain modes (SSE/AVX etc.) have particular cost. That cost may drastically change depending on how the implementation of the hypervisors handles the registers in question.