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Curious, what do you find so bad about them?
by FPGAhacker 5y ago
Curious, what do you find so bad about them?
- rowanG077 5y agoLittle to no IDE support. Arcane or no type systems. Shitty module systems. Inconsistent semantics. High verbosity. Extremely bad tooling. etc etc
- FPGAhacker 5y agoI can agree with verbosity. But VHDL has an extremely strong type system, which comes from its ADA heritage. It’s semantics are also very consistent per my recollection, but it’s been a while. Verilog definitely has looser numeric typing. It tripped up a friend of mine yesterday. I’ve been doing this stuff forever so I don’t think about it much, and I’m grateful for the simplified math it affords. Disagree on IDE support because vscode support for SV at least is pretty nice. And sigasi is still doing well. But I’m old school I guess and prefer vim/nvim. I actually do a hybrid thing where I’ll use nvim in the vscode terminal to do some quick edits for something not In the workspace every now and then. SystemVerilog smoothed over some of the ugliness of verilog, but then bolted on at least three other languages into one with the semantic inconsistencies you mention. Particularly No idea what the rational was there, if any. But I never found it to be a significant barrier to learning. I’ve done experiments with writing an HDL in Clojure that would compile to SV, and it was fun, but it just created a new set of problems. Much better to work in a standardized language warts and all.