3 ms·
Would you be willing to back and try to optimize this for pure output speed? I thought the exact same question, but wondered if FPGA's gate connections are too
by irjustin 5y ago
Would you be willing to back and try to optimize this for pure output speed?
I thought the exact same question, but wondered if FPGA's gate connections are too distant for FizzBuzz to beat 55 GiB/s.
- londons_explore 5y agoWith an FPGA, the speed limit will 100% be how you want to output the data. If you require it to come out of IO pins, then the limit will be the total output bandwidth of all the serdes units on the IO pins. Typically that's much more than 55GiB/s.
- 123pie123 5y agoJust had a quick look at the cheap FPGA dev boards and on my basic search the clock speeds seems to be in the low 1-10GHz range. But this task could be scaled up with parallel FPGA boards in sync
- londons_explore 5y agoIt isn't clock speed that matters, but the number of IO pins and the rate the serdes units can be clocked. Eg. Stratix V GX devices offer up to 66 integrated transceivers with 14.1-Gbps data rate. Thats ~1Tbps right away from a single $500 device.