Have you looked at Chisel? It isn't really high level synthesis but the Chisel is converted to Verilog and then that is synthesized like normal. It makes conn

Have you looked at Chisel? It isn't really high level synthesis but the Chisel is converted to Verilog and then that is synthesized like normal. It makes connecting things and configuration a lot easier. https://en.wikipedia.org/wiki/Chisel_(programming_language) https://en.wikipedia.org/wiki/Chisel_(programming_language) https://www.chisel-lang.org/ https://www.chisel-lang.org/