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One of several tradeoffs is that M1-based stuff has a RAM ceiling, which until a few days ago was 16GB, now it's 64GB. If you need more than that, then you can'
by PostOnce 5y ago
One of several tradeoffs is that M1-based stuff has a RAM ceiling, which until a few days ago was 16GB, now it's 64GB. If you need more than that, then you can't use M1.
Does the performance gap close if Intel starts selling similar on-package RAM to consumers?
I suspect yes, and rapidly. They have it, they just apparently don't want to sell it outside of specialized high-margin goods like Xeon Phi.
- judge2020 5y agoDo board partners want this, though? Apple only has their own margin to worry about, but when Intel starts putting DIMMs on-chip, now the system integrator doesn't know exactly how much Intel's markup is on their CPU versus their memory modules, so they end up surrendering more margin to Intel, even if it's small (eg. paying 5% more dollars per GB with Intel versus sourcing DIMMs yourself).
- ksec 5y ago>Does the performance gap close if Intel starts selling similar on-package RAM to consumers? That assumes on-package RAM is the key to M1 / Apple's SoC performance. And that isn't the case.
- adgjlsfhk1 5y agoIt partially is. The M1 max comes with integrated hbm, which is way higher bandwidth than ddr4. Modern Intel/AMD processors are memory bottlenecked in multicore workloads (hence why 3d cache for Zen is a 15% improvement). The combination of hbm and on package memory means the M1 has much higher bandwidth and similar latency to anything else on the market (at the cost of not being scalable).
- ben-schaaf 5y agoDo you have any source for Apple using HBM? Even the earliest version of HBM back in 2015 had 512GB/s at 4GB. It's probably just LPDDR5.
- ksec 5y agoI really thought I stamp out the "Unified Memory" and "On Package Memory" being the reason why M1 is faster on HN. >The M1 max comes with integrated hbm It is not HBM, just a very wide LPDDR5. >hence why 3d cache for Zen is a 15% improvement Increasing Cache size has nothing to do with Bandwidth. It is the latency and cycle count that matters. >Modern Intel/AMD processors are memory bottlenecked in multicore workloads Depending on Workload. The whole reason why Apple has put those bandwidth in place was because of GPU, which are bandwidth sensitive. The M1 Pro has the same MT performance as M1 Max despite only have half the memory bandwidth. You could have much faster memory on an Intel x86 system, and performance wouldn't even make that much different. Your whole CPU uArch needs to be designed take advantage of the additional bandwidth. Longer pipeline with better prefetch. >and on package memory means the M1 has much higher bandwidth Again. There are no relationship between on package memory and high memory bandwidth. You could have achieve the same with DDR5 with DIMM slot. At the expense of much higher energy usage.
- girvo 5y agoIntel's new Sapphire Rapids is also doing on-package HBM
- floatboth 5y agoIT'S NOT HBM! NEITHER IS APPLE'S MEMORY! Stop spreading this myth, please just look at a Vega GPU die shot and you'll know what HBM looks like. You cannot put HBM on a PCB package. HBM is connected with a silicon interposer.
- girvo 5y agoMy apologies. I even checked some of the press on it before commenting to double check it, and tech press has been calling it that too.