That's only second stage decoding. In the fetch/pre-decode stage there is a specific piece of hardware that partially decodes 16 byte chunks of instruction stre

That's only second stage decoding. In the fetch/pre-decode stage there is a specific piece of hardware that partially decodes 16 byte chunks of instruction streams before inserting instructions into the instruction queue for the decode from macro-op to uop. It can only handle 6 instructions per clock and 16 bytes per clock. If you have 7 instructions in a 16 byte block it takes two cycles to process that block. If you have only 2 instructions in that 16 byte block you only get those two instructions. It also only looks for instruction length and branching to feed the branch predictor, spitting the same instructions back out albeit fused and tagged with index numbers for insertion into the instruction queue ready for the second stage decoders. This is the length that Intel has to go to in order to keep the EUs fed. Apple/ARM? Every 4 bytes there's an instruction.