> Rather instructions were bit encoded in a single memory cell so some could be executed in parallel. I think you might be remembering the later Seaforth/Gree

> Rather instructions were bit encoded in a single memory cell so some could be executed in parallel. I think you might be remembering the later Seaforth/Greenarrays MISC (minimal instruction set computer) chips (they may have had some similar predecessors) that did that funny encoding. The RTX2010 was more like the Novix and had a 16 bit instruction word. See: https://users.ece.cmu.edu/~koopman/stack_computers/sec4_5.html https://users.ece.cmu.edu/~koopman/stack_computers/sec4_5.ht... That book has good coverage of the Forth chips of that era. This undergraduate thesis has some later developments: http://fpgacpu.ca/stack/Second-Generation_Stack_Computer_Architecture.pdf http://fpgacpu.ca/stack/Second-Generation_Stack_Computer_Arc... Related stuff from same site: http://fpgacpu.ca/stack http://fpgacpu.ca/stack