There's few open source tools for any HDL full stop. Indeed I'd say SystemVerilog is doing better on that front, as Verilator (https://www.veripool.org/verilat

There's few open source tools for any HDL full stop. Indeed I'd say SystemVerilog is doing better on that front, as Verilator (https://www.veripool.org/verilator/ https://www.veripool.org/verilator/) supports SystemVerilog and is probably the best open source tool for 'real' HDL work (note the number of industrial users).