I didn't mean open source, no, and it looks like the free version of yosys has limited support of systemverilog. What I meant were the free toolchains provided

I didn't mean open source, no, and it looks like the free version of yosys has limited support of systemverilog. What I meant were the free toolchains provided by all of the FPGA vendors. They typically support SystemVerilog in synthesis and modelsim as far as I have seen.