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Hm, every vendor with free tools (Xilinx/Altera/Lattice/Microsemi etc), seem to be fine with it, along with the usual vendor-specific Modelsim. In fact, most "v
by beefok 5y ago
Hm, every vendor with free tools (Xilinx/Altera/Lattice/Microsemi etc), seem to be fine with it, along with the usual vendor-specific Modelsim. In fact, most "verilog" synthesis tools actually synthesize SystemVerilog. Out of curiosity what tool are you referring to?
Thanks!
- mhh__ 5y agoThere isn't much support if any in open source tools, if free means free software.
- beefok 5y agoI didn't mean open source, no, and it looks like the free version of yosys has limited support of systemverilog. What I meant were the free toolchains provided by all of the FPGA vendors. They typically support SystemVerilog in synthesis and modelsim as far as I have seen.
- gchadwick 5y agoThere's few open source tools for any HDL full stop. Indeed I'd say SystemVerilog is doing better on that front, as Verilator (https://www.veripool.org/verilator/ https://www.veripool.org/verilator/) supports SystemVerilog and is probably the best open source tool for 'real' HDL work (note the number of industrial users).