And that's why Verilog has mostly "won". But syntax isn't the whole story of a language. VHDL's type system is much superior to Verilog's. I once worked for an

And that's why Verilog has mostly "won". But syntax isn't the whole story of a language. VHDL's type system is much superior to Verilog's. I once worked for an EDA company and we had a product that emitted HDL (Verilog or VHDL depending on what the user chose). At some point we had requests from customers to fix linting warnings in the generated code. My job was to placate the linter. For the VHDL code generator there wasn't much to fix - just not a lot of linting problems due to the type system. For the verilog code generator, though, there were lots of linting warnings to fix.