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I was gonna say something similar. VHDL’s type system for starters is way better (thanks to it being based off Ada) While not a big fan of the begin end style
by anfilt 5y ago
I was gonna say something similar. VHDL’s type system for starters is way better (thanks to it being based off Ada)
While not a big fan of the begin end style syntax, it definitely is better than verilog in my experience.
I find interesting so many open source projects like this target Verilog. It also kinda bugs me.
- dnautics 5y agoat the same time, if you're transpiling from something else, verilog is MUCH better than VHDL because as a language it has a much smaller surface area. Modulo "HDL is different because everything is synchronous" and the testing DSL, You can learn most of verilog in a day, not so much VHDL.