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SystemVerilog also supports composite types using interfaces. Using Verilator as a linter will aggressively warn you about signal width mismatches. Most compl
by brandmeyer 5y ago
SystemVerilog also supports composite types using interfaces. Using Verilator as a linter will aggressively warn you about signal width mismatches.
Most complaints about Verilog from VHDL people come from outdated notions of the current state of the language and its tooling.
- WillFlux 5y agoI also have a post on Verilog Lint with Verilator: https://projectf.io/posts/verilog-lint-with-verilator/ https://projectf.io/posts/verilog-lint-with-verilator/
- anfilt 5y agoVHDLs type system is pretty rock solid it’s based off Ada after all. Which if you have looked at in any detail its a great type system! I dont like the begin end style syntax and some the verbosity that entails with VHDL. However, I would rather create designs in VHDL than verilog when given the choice.