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VHDL has horrible syntax. Verilog has a much more friendly c-like syntax, even if the friendliness is only a trap.
by aortega 5y ago
VHDL has horrible syntax. Verilog has a much more friendly c-like syntax, even if the friendliness is only a trap.
- Arch-TK 5y agoI imagine you think pascal and ada have horrible syntax too? For me, the syntax is ideal. On the plus side VHDL seems to have actually been designed with the intention of being used for FPGA designs. Verilog on the other hand just seems like a hack in comparison.
- leche 5y agoThe opposite is true. VHDL was originally designed as an implementation-agnostic documentation and description language.
- UncleOxidant 5y agoAnd that's why Verilog has mostly "won". But syntax isn't the whole story of a language. VHDL's type system is much superior to Verilog's. I once worked for an EDA company and we had a product that emitted HDL (Verilog or VHDL depending on what the user chose). At some point we had requests from customers to fix linting warnings in the generated code. My job was to placate the linter. For the VHDL code generator there wasn't much to fix - just not a lot of linting problems due to the type system. For the verilog code generator, though, there were lots of linting warnings to fix.