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To me, it looks like Intel is playing catch up, and trying every heroic hack like HBM that they can think of in order to be competitive with AMD. It reminds me

To me, it looks like Intel is playing catch up, and trying every heroic hack like HBM that they can think of in order to be competitive with AMD. It reminds me a lot of the last days of Netburst, with heroic hacks like huge (for the time) caches, high clock speeds, and then bumping up against TDP limits.

kingosticks 5y ago
This is for a supercomputer, right? Do AMD have something for Intel to compete against here?
speed_spread 5y ago
The P4 high clock speeds were not a hack, they were the root of the problem. High clock speeds were an architectural constraint driven by the _marketing_ department. Intel's architect knew that this wasn't the way to go for actual performance but delivered what was asked of them.
- toast0 5y ago
  > High clock speeds were an architectural constraint driven by the _marketing_ department. High clock speeds are an architectural constraint driven by the market. Intel and AMD can't sell chips that don't clock high in laptops and desktops and they can't afford to specialize much for mid-clocked server chips, so they need a design that can at least approach 5GHz for boost clocks. Instructions per Clock matters too, but the market would have a hard time buying an x86 chip that stopped at 3 GHz, even if it was double the IPC. That means they can't make a super-wide processor like Apple that tops out around 3 GHz, where Apple is more comfortable providing sufficient cooling.
  - theevilsharpie 5y ago
    > Instructions per Clock matters too, but the market would have a hard time buying an x86 chip that stopped at 3 GHz, even if it was double the IPC. AMD's response to the later-life Pentium 4's was the Athlon 64, which was clocked substantially lower but matched or beat the P4 in most tasks. The market responded positively. Similarly, the original Pentium was clocked substantially lower than high end 486 models when it was first introduced. It was also received positively. In modern times, the market has responded positively to the Apple M1. Has there actually been a CPU anywhere that has outperformed its market competitor (in price and performance), but failed to gain traction because its clock speed was too low? "The market wants high clock speeds" has been a common assumption, but I've never actually seen it work out that way in practice.
bertr4nd 5y ago
This product is competing against NVidia for the deep learning space, not AMD. NV’s A100 features enormous memory bandwidth (1.4 TB/s) thanks to HBM and peak flops (300 TFlops/s) thanks to tensor cores, so using HBM and Advanced Matrix Extensions here is pretty clearly aimed at that segment.
celrod 5y ago
Golden cove core highlights[1] include a 6 wide decoder (up from 4; M1 is 8), reorder buffer of 512 (up from 352 in Ice/Tiger/Rocket lake, or 224 in Skylake; M1 is estimated around 650), and 12 execution units (up from 10 in Ice/Tiger/Rocket lake or 8 in Skylake). Still not as wide as the M1, but it looks like a huge step in the right direction on paper. [1] https://en.wikipedia.org/wiki/Golden_Cove https://en.wikipedia.org/wiki/Golden_Cove

kingosticks 5y ago

This is for a supercomputer, right? Do AMD have something for Intel to compete against here?

speed_spread 5y ago

The P4 high clock speeds were not a hack, they were the root of the problem. High clock speeds were an architectural constraint driven by the _marketing_ department. Intel's architect knew that this wasn't the way to go for actual performance but delivered what was asked of them.

toast0 5y ago
> High clock speeds were an architectural constraint driven by the _marketing_ department. High clock speeds are an architectural constraint driven by the market. Intel and AMD can't sell chips that don't clock high in laptops and desktops and they can't afford to specialize much for mid-clocked server chips, so they need a design that can at least approach 5GHz for boost clocks. Instructions per Clock matters too, but the market would have a hard time buying an x86 chip that stopped at 3 GHz, even if it was double the IPC. That means they can't make a super-wide processor like Apple that tops out around 3 GHz, where Apple is more comfortable providing sufficient cooling.
- theevilsharpie 5y ago
  > Instructions per Clock matters too, but the market would have a hard time buying an x86 chip that stopped at 3 GHz, even if it was double the IPC. AMD's response to the later-life Pentium 4's was the Athlon 64, which was clocked substantially lower but matched or beat the P4 in most tasks. The market responded positively. Similarly, the original Pentium was clocked substantially lower than high end 486 models when it was first introduced. It was also received positively. In modern times, the market has responded positively to the Apple M1. Has there actually been a CPU anywhere that has outperformed its market competitor (in price and performance), but failed to gain traction because its clock speed was too low? "The market wants high clock speeds" has been a common assumption, but I've never actually seen it work out that way in practice.

bertr4nd 5y ago

This product is competing against NVidia for the deep learning space, not AMD. NV’s A100 features enormous memory bandwidth (1.4 TB/s) thanks to HBM and peak flops (300 TFlops/s) thanks to tensor cores, so using HBM and Advanced Matrix Extensions here is pretty clearly aimed at that segment.

celrod 5y ago

Golden cove core highlights[1] include a 6 wide decoder (up from 4; M1 is 8), reorder buffer of 512 (up from 352 in Ice/Tiger/Rocket lake, or 224 in Skylake; M1 is estimated around 650), and 12 execution units (up from 10 in Ice/Tiger/Rocket lake or 8 in Skylake). Still not as wide as the M1, but it looks like a huge step in the right direction on paper. [1] https://en.wikipedia.org/wiki/Golden_Cove https://en.wikipedia.org/wiki/Golden_Cove