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Here is one meaning: Intel microcode updates added new machine opcodes to address spectre/meltdown exploits. On a true RISC, that's not possible.
by chasil 5y ago
Here is one meaning:
Intel microcode updates added new machine opcodes to address spectre/meltdown exploits.
On a true RISC, that's not possible.
- dragontamer 5y agohttps://www.zdnet.com/article/meltdown-spectre-ibm-preps-firmware-and-os-fixes-for-vulnerable-power-cpus/ https://www.zdnet.com/article/meltdown-spectre-ibm-preps-fir... Or are you going to argue that the venerable POWER-architecture is somehow not "true RISC" ?? https://www.ibm.com/support/pages/checking-aix-protection-against-spectre-and-meltdown-settings https://www.ibm.com/support/pages/checking-aix-protection-ag...
- chasil 5y agoIf its got microcode, it's not RISC.
- dragontamer 5y agoPOWER9, RISC-V, and ARM all have microcoded instructions. In particular, division, which is very complicated. As all CPUs have decided that hardware-accelerated division is a good idea (and in particular: microcoded, single-instruction division makes more sense than spending a bunch of L1 cache on a series of instructions that everyone knows is "just division" and/or "modulo"), microcode just makes sense. The "/" and "%" operators are just expected on any general purpose CPU these days. 30 years ago, RISC processors didn't implement divide or modulo. Today, all processors, even the "RISC" ones, implement it.