3 ms·
Don’t think that is entirely true. Lots of features which exist on both RISC and CISC CPUs have different natural fit. Using micro-ops e.g. on a CISC is more im
by socialdemocrat 5y ago
Don’t think that is entirely true. Lots of features which exist on both RISC and CISC CPUs have different natural fit. Using micro-ops e.g. on a CISC is more important than in RISC CPU even if both benefit. Likewise pipelining has a more natural fit on RISC than CISC, while micro-op cache is more important on CISC than RISC.
- dragontamer 5y agoI don't even know what RISC or CISC means anymore. They're bad, non-descriptive terms. 30 years ago, RISC or CISC meant something, but not anymore. Today's CPUs are pipelined, out-of-order, speculative, superscalar, (sometimes) SMT, SIMD, multi-core with MESI-based snooping for cohesive caches. These words actually have meaning (and in particular, describe a particular attribute of performance for modern cores). RISC or CISC? useful for internet flamewars I guess but I've literally never been able to use either term in a technical discussion. ------- I said what I said earlier: this M1 Pro / M1 Max, and the ARM Neoverse cores, are missing SMT, which seems to come standard on every other server-class CPU (POWER9, Intel Skylake-X, AMD EPYC). Neoverse N1 makes up for it with absurdly high core counts, so maybe its not a big deal. Apple M1 however has very small core counts, I doubt that Apple M1 would be good in a server setting... at least not with this configuration. They'd have to change things dramatically to compete at the higher end.
- chasil 5y agoHere is one meaning: Intel microcode updates added new machine opcodes to address spectre/meltdown exploits. On a true RISC, that's not possible.
- dragontamer 5y agohttps://www.zdnet.com/article/meltdown-spectre-ibm-preps-firmware-and-os-fixes-for-vulnerable-power-cpus/ https://www.zdnet.com/article/meltdown-spectre-ibm-preps-fir... Or are you going to argue that the venerable POWER-architecture is somehow not "true RISC" ?? https://www.ibm.com/support/pages/checking-aix-protection-against-spectre-and-meltdown-settings https://www.ibm.com/support/pages/checking-aix-protection-ag...
- chasil 5y agoIf its got microcode, it's not RISC.
- dragontamer 5y agoPOWER9, RISC-V, and ARM all have microcoded instructions. In particular, division, which is very complicated. As all CPUs have decided that hardware-accelerated division is a good idea (and in particular: microcoded, single-instruction division makes more sense than spending a bunch of L1 cache on a series of instructions that everyone knows is "just division" and/or "modulo"), microcode just makes sense. The "/" and "%" operators are just expected on any general purpose CPU these days. 30 years ago, RISC processors didn't implement divide or modulo. Today, all processors, even the "RISC" ones, implement it.
- floatboth 5y agoToday RISC just means an ISA is fixed-length load-store. No uarch implications.