5 ms·

Why? There are plenty of server oriented ARM platforms available for use (See AWS Graviton). What benefit do you feel Apple’s platform gives over existing ones?

dragontamer 5y ago
The Apple cores are full custom, Apple-only designs. The AWS Graviton are Neoverse cores, which are pretty good, but clearly these Apple-only M1 cores are above-and-beyond. --------- That being said: these M1 cores (and Neoverse cores) are missing SMT / Hyperthreading, and a few other features I'd expect in a server product. Servers are fine with the bandwidth/latency tradeoff: more (better) bandwidth but at worse (highter) latencies.
- lillecarl 5y ago
  My understanding is that you don't really need hyperthreading on a RISC CPU because decoding instructions is easier and doesn't have to be parallelised as with hyperthreading.
  - dragontamer 5y ago
    Okay, the whole RISC thing is stupid. But ignoring that aspect of the discussion... POWER9, one of those RISC CPUs, has 8-way SMT. Neoverse E1 also has SMT-2 (aka: 2-way hyperthreading). SMT / Hyperthreading has nothing to do with RISC / CISC or whatever. Its just a feature some people like or don't like. RISC CPUs (Neoverse E1 / POWER9) can perfectly do SMT if the designers wanted.
    - socialdemocrat 5y ago
      Don’t think that is entirely true. Lots of features which exist on both RISC and CISC CPUs have different natural fit. Using micro-ops e.g. on a CISC is more important than in RISC CPU even if both benefit. Likewise pipelining has a more natural fit on RISC than CISC, while micro-op cache is more important on CISC than RISC.
      - dragontamer 5y ago
        I don't even know what RISC or CISC means anymore. They're bad, non-descriptive terms. 30 years ago, RISC or CISC meant something, but not anymore. Today's CPUs are pipelined, out-of-order, speculative, superscalar, (sometimes) SMT, SIMD, multi-core with MESI-based snooping for cohesive caches. These words actually have meaning (and in particular, describe a particular attribute of performance for modern cores). RISC or CISC? useful for internet flamewars I guess but I've literally never been able to use either term in a technical discussion. ------- I said what I said earlier: this M1 Pro / M1 Max, and the ARM Neoverse cores, are missing SMT, which seems to come standard on every other server-class CPU (POWER9, Intel Skylake-X, AMD EPYC). Neoverse N1 makes up for it with absurdly high core counts, so maybe its not a big deal. Apple M1 however has very small core counts, I doubt that Apple M1 would be good in a server setting... at least not with this configuration. They'd have to change things dramatically to compete at the higher end.
        chasil 5y ago
        Here is one meaning: Intel microcode updates added new machine opcodes to address spectre/meltdown exploits. On a true RISC, that's not possible.
        dragontamer 5y ago
        https://www.zdnet.com/article/meltdown-spectre-ibm-preps-firmware-and-os-fixes-for-vulnerable-power-cpus/ https://www.zdnet.com/article/meltdown-spectre-ibm-preps-fir... Or are you going to argue that the venerable POWER-architecture is somehow not "true RISC" ?? https://www.ibm.com/support/pages/checking-aix-protection-against-spectre-and-meltdown-settings https://www.ibm.com/support/pages/checking-aix-protection-ag...
        chasil 5y ago
        If its got microcode, it's not RISC.
        5y ago
  - chasil 5y ago
    The DEC Alpha had SMT on their processor roadmap, but it was never implemented as their own engineers told the Compaq overlords that they could never compete with Intel. "The 21464's origins began in the mid-1990s when computer scientist Joel Emer was inspired by Dean Tullsen's research into simultaneous multithreading (SMT) at the University of Washington." https://en.wikipedia.org/wiki/Alpha_21464 https://en.wikipedia.org/wiki/Alpha_21464
  - tedunangst 5y ago
    Hyper threading has nothing to do with instruction decode. It's for hiding memory latency. The sparc T line is 8 way threaded.
    - monocasa 5y ago
      It's slightly more general than that, hiding inefficient use of functional units. A lot of times that's totally memory latency causing the inability to keep FUs fed like you say, but i've seen other reasons, like a wide but diverse set of FUs that have trouble applying to every workload.
      - mnw21cam 5y ago
        The classic reason quoted for SMT is to allow the functional units to be fully utilised when there is instruction-to-instruction dependencies - that is, the input of one instruction is the output from the previous instruction. Doing SMT allow you to create one large pool of functional units and share them between multiple threads, hopefully increasing the chances that they will be fully used.
modulusshift 5y ago
Well, tons, there isn't another ARM core that can match a single M1 Firestorm, core to core. Heck, only the highest performance x86 cores can match a Firestorm core. and that's just raw performance, not even considering power efficiency. But of course, Apple's not sharing.

dragontamer 5y ago

The Apple cores are full custom, Apple-only designs. The AWS Graviton are Neoverse cores, which are pretty good, but clearly these Apple-only M1 cores are above-and-beyond. --------- That being said: these M1 cores (and Neoverse cores) are missing SMT / Hyperthreading, and a few other features I'd expect in a server product. Servers are fine with the bandwidth/latency tradeoff: more (better) bandwidth but at worse (highter) latencies.

lillecarl 5y ago
My understanding is that you don't really need hyperthreading on a RISC CPU because decoding instructions is easier and doesn't have to be parallelised as with hyperthreading.
- dragontamer 5y ago
  Okay, the whole RISC thing is stupid. But ignoring that aspect of the discussion... POWER9, one of those RISC CPUs, has 8-way SMT. Neoverse E1 also has SMT-2 (aka: 2-way hyperthreading). SMT / Hyperthreading has nothing to do with RISC / CISC or whatever. Its just a feature some people like or don't like. RISC CPUs (Neoverse E1 / POWER9) can perfectly do SMT if the designers wanted.
  - socialdemocrat 5y ago
    Don’t think that is entirely true. Lots of features which exist on both RISC and CISC CPUs have different natural fit. Using micro-ops e.g. on a CISC is more important than in RISC CPU even if both benefit. Likewise pipelining has a more natural fit on RISC than CISC, while micro-op cache is more important on CISC than RISC.
    - dragontamer 5y ago
      I don't even know what RISC or CISC means anymore. They're bad, non-descriptive terms. 30 years ago, RISC or CISC meant something, but not anymore. Today's CPUs are pipelined, out-of-order, speculative, superscalar, (sometimes) SMT, SIMD, multi-core with MESI-based snooping for cohesive caches. These words actually have meaning (and in particular, describe a particular attribute of performance for modern cores). RISC or CISC? useful for internet flamewars I guess but I've literally never been able to use either term in a technical discussion. ------- I said what I said earlier: this M1 Pro / M1 Max, and the ARM Neoverse cores, are missing SMT, which seems to come standard on every other server-class CPU (POWER9, Intel Skylake-X, AMD EPYC). Neoverse N1 makes up for it with absurdly high core counts, so maybe its not a big deal. Apple M1 however has very small core counts, I doubt that Apple M1 would be good in a server setting... at least not with this configuration. They'd have to change things dramatically to compete at the higher end.
      - chasil 5y ago
        Here is one meaning: Intel microcode updates added new machine opcodes to address spectre/meltdown exploits. On a true RISC, that's not possible.
        dragontamer 5y ago
        https://www.zdnet.com/article/meltdown-spectre-ibm-preps-firmware-and-os-fixes-for-vulnerable-power-cpus/ https://www.zdnet.com/article/meltdown-spectre-ibm-preps-fir... Or are you going to argue that the venerable POWER-architecture is somehow not "true RISC" ?? https://www.ibm.com/support/pages/checking-aix-protection-against-spectre-and-meltdown-settings https://www.ibm.com/support/pages/checking-aix-protection-ag...
        chasil 5y ago
        If its got microcode, it's not RISC.
        5y ago
- chasil 5y ago
  The DEC Alpha had SMT on their processor roadmap, but it was never implemented as their own engineers told the Compaq overlords that they could never compete with Intel. "The 21464's origins began in the mid-1990s when computer scientist Joel Emer was inspired by Dean Tullsen's research into simultaneous multithreading (SMT) at the University of Washington." https://en.wikipedia.org/wiki/Alpha_21464 https://en.wikipedia.org/wiki/Alpha_21464
- tedunangst 5y ago
  Hyper threading has nothing to do with instruction decode. It's for hiding memory latency. The sparc T line is 8 way threaded.
  - monocasa 5y ago
    It's slightly more general than that, hiding inefficient use of functional units. A lot of times that's totally memory latency causing the inability to keep FUs fed like you say, but i've seen other reasons, like a wide but diverse set of FUs that have trouble applying to every workload.
    - mnw21cam 5y ago
      The classic reason quoted for SMT is to allow the functional units to be fully utilised when there is instruction-to-instruction dependencies - that is, the input of one instruction is the output from the previous instruction. Doing SMT allow you to create one large pool of functional units and share them between multiple threads, hopefully increasing the chances that they will be fully used.

modulusshift 5y ago

Well, tons, there isn't another ARM core that can match a single M1 Firestorm, core to core. Heck, only the highest performance x86 cores can match a Firestorm core. and that's just raw performance, not even considering power efficiency. But of course, Apple's not sharing.