The problem was solved in the end of the C64's commercial life - the SuperCPU adds a 20MHz 65816, and using memory mirroring and wait states when accessing the

The problem was solved in the end of the C64's commercial life - the SuperCPU adds a 20MHz 65816, and using memory mirroring and wait states when accessing the 1MHz bus, it indeed effectively gives you nearly the full 20MHz in non-I/O situations, and even in I/O situations, the CPU can, with appropriate code, execute several cycles of instructions between 1MHz I/O accesses. The SuperCPU is the only way that I know of on the C64 to be able to literally write a new value to a memory location or chip register on every single 1MHz cycle.