3 ms·

So that's a big problem for the some of the big 6502-based computers and video game systems of the 80s, if you ever wanted a 100Mhz Commodore 64 or NES for exam

So that's a big problem for the some of the big 6502-based computers and video game systems of the 80s, if you ever wanted a 100Mhz Commodore 64 or NES for example. Those systems had more than 64K of addressable items, and various techniques were used to map regions in and out of the 64K 6502 address space. Commodore 64, for example, has 64Kbytes of RAM, 16K of OS and BASIC ROM, 4K of memory mapped I/O, and 4K of character generator ROM. A register at memory location 1 controls what's visible at a given moment. By default you have 40Kbyte of RAM visible along with the ROM and I/O devices. Certain games like Impossible Mission will turn off the ROMs and I/O devices at various times to get at all the RAM "underneath." NES is even more of a mess. The original Super Mario Bros. and a fair amount of "NROM" games fit in to less than 32KByte of ROM, which is by default all that's available to ROM on that platform. Then "mapper" ASICs appeared and there are well over a hundred, and that's a challenge to anyone who wants to implement an NES emulator - emulating all the mappers that had to be reverse engineered. Some are common like the MMC1 and 3 and some are unique to specific games. Now I can see it working in the Apple II because the original platform I think had 16K of RAM, with the possibility to upgrade to 48K of RAM, and 8K of ROM near the top. BASIC was always loaded in from tape or disk. Video was writing to framebuffer and straightforward. You did have 128K Apple systems which came later but plenty of software that would work on an unexpanded Apple. Still awesome though.

LocalH 5y ago
The problem was solved in the end of the C64's commercial life - the SuperCPU adds a 20MHz 65816, and using memory mirroring and wait states when accessing the 1MHz bus, it indeed effectively gives you nearly the full 20MHz in non-I/O situations, and even in I/O situations, the CPU can, with appropriate code, execute several cycles of instructions between 1MHz I/O accesses. The SuperCPU is the only way that I know of on the C64 to be able to literally write a new value to a memory location or chip register on every single 1MHz cycle.

LocalH 5y ago

The problem was solved in the end of the C64's commercial life - the SuperCPU adds a 20MHz 65816, and using memory mirroring and wait states when accessing the 1MHz bus, it indeed effectively gives you nearly the full 20MHz in non-I/O situations, and even in I/O situations, the CPU can, with appropriate code, execute several cycles of instructions between 1MHz I/O accesses. The SuperCPU is the only way that I know of on the C64 to be able to literally write a new value to a memory location or chip register on every single 1MHz cycle.