It should be. Looks like bog-standard verilog to me. It just implements the standard 6502 bus rather than something like AXI or wishbone. (link pulled from the

It should be. Looks like bog-standard verilog to me. It just implements the standard 6502 bus rather than something like AXI or wishbone. (link pulled from the references section of the post) https://github.com/hoglet67/CoPro6502/tree/master/src/Arlet https://github.com/hoglet67/CoPro6502/tree/master/src/Arlet