5 ms·

Way back in 2003 or so, we at my old company InformAsic designed a single chip transparent VPN solution for serial communication (RS-232, RS-422). The control

Way back in 2003 or so, we at my old company InformAsic designed a single chip transparent VPN solution for serial communication (RS-232, RS-422). The control and protocol handling part of the was a modified 6502 core with a sort of MMU and single cycle zero page registers. The whole thing was clocked at 33 MHz, probably making it the fastest 6502 in production at that time. Not that we sold that many of the devices... As an old c64 scener, I really enjoyed being able to code the application SW using my favorite ASM tools. Though most of the code we actually compiled from C using cc65 and then hand tuned to fit the mem constraints. Today a simple Cortex M0+ MCU (with internal AES core) would be able to do what we did, and probably be smaller and require less power.

klelatti 5y ago
Out of curiosity, how does an M0+ + MCU manage to be smaller and more power efficient than something as simple as a 6502?
- compiler-guy 5y ago
  The 6502 isn’t manufactured with modern processes and technology. It’s still stuck in the eighties for that sort of thing. So basically everything even a few years newer will be smaller and more power efficient.
  - klelatti 5y ago
    Of course an M0 on a modern process node would be much smaller but I’d interpreted (probably wrongly) the OP as going further and saying that the M0 would be smaller on a comparable node. With 12k or so gates on an M0 that doesn’t seem possible although maybe modern power management would make it more power efficient.
    - JoachimS 5y ago
      No, that is not at all what I meant. But I agree that I could have been more clear.
- JoachimS 5y ago
  ASIC process generations. The original MOS 6502 was manufactured in really big process - when "Contact" actually meant making contact on the plastic sheets that became the masks. Huge transistors, 5V power supply etc. Modern Cortex M0+ chips are probably manufactured using 90nm, 65nm process nodes (or possibly even smaller - but the die size will become I/O-bound. Though you can then add more memory easily without driving up the die size). They have much lower core supply, much better I/Os - and low power modes. In our specific case, we used I believe 250 nm, or possibly even 350 nm ASIC process. And size in this specific case also related to the package. We used a QFN. Today you can get a M0+ based MCU with low number of exposed I/Os in a small BGA or WCP packages that is just a few mm2. The idea we had at the start was a chip small enough to fit inside the connector of a serial wire, require so little power to not need external power (basically harvesting), be fast enough to not reduce bitrate. Add very low and fixed latency. And be transparent to (after configuration) be totally transparent as seen from the application. Basically a secure serial cable. But reduced to be an extra cable connector that is inserted between an IoT, SCADA device and its serially connected modem. Due to the process node we didn't really get there. But today this is basically feasible using off-the-shelf MCUs. I actually found a few of the chips and one of the cable connectors/dongles Yesterday. So I still have a few 33 MHz 6502s ;-)
  - klelatti 5y ago
    Thanks for a really comprehensive reply - very interesting.

klelatti 5y ago

Out of curiosity, how does an M0+ + MCU manage to be smaller and more power efficient than something as simple as a 6502?

compiler-guy 5y ago
The 6502 isn’t manufactured with modern processes and technology. It’s still stuck in the eighties for that sort of thing. So basically everything even a few years newer will be smaller and more power efficient.
- klelatti 5y ago
  Of course an M0 on a modern process node would be much smaller but I’d interpreted (probably wrongly) the OP as going further and saying that the M0 would be smaller on a comparable node. With 12k or so gates on an M0 that doesn’t seem possible although maybe modern power management would make it more power efficient.
  - JoachimS 5y ago
    No, that is not at all what I meant. But I agree that I could have been more clear.
JoachimS 5y ago
ASIC process generations. The original MOS 6502 was manufactured in really big process - when "Contact" actually meant making contact on the plastic sheets that became the masks. Huge transistors, 5V power supply etc. Modern Cortex M0+ chips are probably manufactured using 90nm, 65nm process nodes (or possibly even smaller - but the die size will become I/O-bound. Though you can then add more memory easily without driving up the die size). They have much lower core supply, much better I/Os - and low power modes. In our specific case, we used I believe 250 nm, or possibly even 350 nm ASIC process. And size in this specific case also related to the package. We used a QFN. Today you can get a M0+ based MCU with low number of exposed I/Os in a small BGA or WCP packages that is just a few mm2. The idea we had at the start was a chip small enough to fit inside the connector of a serial wire, require so little power to not need external power (basically harvesting), be fast enough to not reduce bitrate. Add very low and fixed latency. And be transparent to (after configuration) be totally transparent as seen from the application. Basically a secure serial cable. But reduced to be an extra cable connector that is inserted between an IoT, SCADA device and its serially connected modem. Due to the process node we didn't really get there. But today this is basically feasible using off-the-shelf MCUs. I actually found a few of the chips and one of the cable connectors/dongles Yesterday. So I still have a few 33 MHz 6502s ;-)
- klelatti 5y ago
  Thanks for a really comprehensive reply - very interesting.