3 ms·
The boards are different but the chip has the same markings as the chip on this board running AOSP on RISC-V. https://github.com/T-head-Semi/aosp-riscv https:/
by brucehoult 5y ago
The boards are different but the chip has the same markings as the chip on this board running AOSP on RISC-V.
https://github.com/T-head-Semi/aosp-riscv https://github.com/T-head-Semi/aosp-riscv
So it should have a 3rd RV64GC + Vector draft 0.7.1 core capable of 2 128 bit vector ALU operations, 1 vector load, 1 vector store per cycle.