Atomic operations (atomic ind/dec) can still cause major performance issues because depending on the architecture it can cause a lot of bus traffic and cache in

Atomic operations (atomic ind/dec) can still cause major performance issues because depending on the architecture it can cause a lot of bus traffic and cache invalidation which can greatle increase memory pressure for previously cached operations.. a better solution would be to use a more cache friendly counter that puts multiple counter on different cache lines and lazily reconciles them so you only need to synchronize one out of n operations, the problem is that this can cause a big increase in memory usage so its only suitable for highly contended locks. The ideal situation would be for the intepreter to analyse contended locks and then switch to this approach only when neccesay. The technique is called sloppy counter and has been used in linux smp kernels.