6 ms·

At what point does quantum tunnelling become a problem?

codefined 5y ago
Quantum tunnelling has already become a problem in most computer components. NAND flash was the first in maybe 2015 to start reporting seeing issues? Effects are moderately visible and have to be counteracted at 5nm. I heard some rumours about 7nm, but cannot confirm any countermeasures were taken to avoid quantum effects. It should be noted that "3nm" is now purely for commercial reasons and has no relationship to the size of transistors on board.
wetpaws 5y ago
It's always been a problem to some degree. Keep in mind that 3nm is a misnomer and has no real physical meaning behind it.
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weatherlight 5y ago
First though, "5nm", "3nm" and so on are just marketing names. There is nothing about "5nm" that makes it "5nm" other than the company in question saying it is. Some things are smaller than 5nm on a given 5nm node, and some are larger. I cannot recall exactly what node this started to be the case (there used to be an actual definition, one for DRAM, one for logic), but it was in the past two decades and got particularly ridiculous beginning around "28nm" up to now. The really concerning physical dimension for quantum tunneling to occur/not occur is "gate length," and that's been basically sitting around ~16nm (actual, real, literal 16nm), plus or minus a few nanometers (depending on the manufacturer and process in question), since about "45nm" (mid-late 2000s). So that one critical dimension isn't getting smaller. And there isn't much they can do about it right now. They are still shrinking other dimensions though, and things don't work like they used to. Powered off transistors aren't really off, and leak power. The workaround for this is that they just use bigger transistors in certain places for what's called "power gating". You get the benefits of having tons of small transistors, with a slight area penalty. In addition to power gating, they have made substantial improvements to the design of the transistors themselves. Gates now wrap around the channel on 3 sides, creating a device known as a Finfet. Silicon dioxide is no longer used as an insulator to the same extent -- hafnium dioxide preforms much better as an insulator. Gates are now metal instead of polysilicon. And there's an assortment of other changes that have occurred or are on the way. So performance has actually managed to improve somewhat, and things have still gotten smaller. The end is near... but not quite yet. Gate length is not going to budge much unless some miracle occurs, though.
- baybal2 5y ago
  The theoretical half pitch size limit for a single exposure EUV is Lambda * 2 or 26nm. You can get arbitrarily small at the cost of exploding count of masks. I.E. double patterning needs 2X masks, but quad patterning needs 8X. Octuple patterning is completely impractical.
  - Misdicorl 5y ago
    Can't they use a smaller wavelength source? Nothing special about 13nm afaik
    - baybal2 5y ago
      13nm * 2 is 26nm. Using a smaller wavelength is kind of useless for the optical lithography, as below this photons will make too many secondary electrons which will reduce the effective resolution. This is the reason X-ray lithography went nowhere. This is why the ultimate limit of 157nm lithography was also not so far away from EUV. Also somewhere in between 25nm-30nm This is also why some people suggest resurrecting 157nm — getting nearly same half pitch without maintenance, and expensive tooling of EUV.
    - Filligree 5y ago
      The design of EUV lasers is already completely absurd. It's an awesome piece of engineering, but it's no easier to push the laser wavelength downwards than anything else.
      - Misdicorl 5y ago
        Does the lithography require the tight wavelength or other nice properties of lasers? I had thought they used filtered synchrotron output since a while ago. Basically everything about the process is absurd, not sure why pushing on the light source is less feasible then any of the other knobs
        lazide 5y ago
k0stas 5y ago
It already has been a problem in terms of gate leakage, although largely mitigated by material improvements. Gate leakage is the phenomenon of quantum tunneling through the gate dielectric barrier and started appearing as gate dielectrics became thinner and thinner. Gate leakage was mitigated by moving to higher k dielectrics (from silicon dioxide, SiO2, to more exotic materials that include other elements such as Hafnium). Higher k dielectrics allow for the same capacitance per unit area and channel control with a thicker physical gate compared to plain SiO2, reducing gate leakage. This technology change came along with metal gates (which used to be polysilicon) and were a combined advance that Intel incorporated a few years before before TSMC, IIRC circa 2008. This is a circuit designer's perspective. Someone who actually understands device physics and material properties can chime in to correct me.
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- baybal2 5y ago
  Your nickname rings familiar. Ex-Xilinx by any chance?
- istarial 5y ago
  Do you have any books that you recommend on this topic? would love to get my hands dirty to the degree that i can with this
hajile 5y ago
From a few years ago until we perfect the QFET and can put it to use.

Quantum tunnelling has already become a problem in most computer components. NAND flash was the first in maybe 2015 to start reporting seeing issues? Effects are moderately visible and have to be counteracted at 5nm. I heard some rumours about 7nm, but cannot confirm any countermeasures were taken to avoid quantum effects. It should be noted that "3nm" is now purely for commercial reasons and has no relationship to the size of transistors on board.

wetpaws 5y ago

It's always been a problem to some degree. Keep in mind that 3nm is a misnomer and has no real physical meaning behind it.

deleted 5y ago
[deleted]

deleted 5y ago

[deleted]

weatherlight 5y ago

First though, "5nm", "3nm" and so on are just marketing names. There is nothing about "5nm" that makes it "5nm" other than the company in question saying it is. Some things are smaller than 5nm on a given 5nm node, and some are larger. I cannot recall exactly what node this started to be the case (there used to be an actual definition, one for DRAM, one for logic), but it was in the past two decades and got particularly ridiculous beginning around "28nm" up to now. The really concerning physical dimension for quantum tunneling to occur/not occur is "gate length," and that's been basically sitting around ~16nm (actual, real, literal 16nm), plus or minus a few nanometers (depending on the manufacturer and process in question), since about "45nm" (mid-late 2000s). So that one critical dimension isn't getting smaller. And there isn't much they can do about it right now. They are still shrinking other dimensions though, and things don't work like they used to. Powered off transistors aren't really off, and leak power. The workaround for this is that they just use bigger transistors in certain places for what's called "power gating". You get the benefits of having tons of small transistors, with a slight area penalty. In addition to power gating, they have made substantial improvements to the design of the transistors themselves. Gates now wrap around the channel on 3 sides, creating a device known as a Finfet. Silicon dioxide is no longer used as an insulator to the same extent -- hafnium dioxide preforms much better as an insulator. Gates are now metal instead of polysilicon. And there's an assortment of other changes that have occurred or are on the way. So performance has actually managed to improve somewhat, and things have still gotten smaller. The end is near... but not quite yet. Gate length is not going to budge much unless some miracle occurs, though.

baybal2 5y ago
The theoretical half pitch size limit for a single exposure EUV is Lambda * 2 or 26nm. You can get arbitrarily small at the cost of exploding count of masks. I.E. double patterning needs 2X masks, but quad patterning needs 8X. Octuple patterning is completely impractical.
- Misdicorl 5y ago
  Can't they use a smaller wavelength source? Nothing special about 13nm afaik
  - baybal2 5y ago
    13nm * 2 is 26nm. Using a smaller wavelength is kind of useless for the optical lithography, as below this photons will make too many secondary electrons which will reduce the effective resolution. This is the reason X-ray lithography went nowhere. This is why the ultimate limit of 157nm lithography was also not so far away from EUV. Also somewhere in between 25nm-30nm This is also why some people suggest resurrecting 157nm — getting nearly same half pitch without maintenance, and expensive tooling of EUV.
  - Filligree 5y ago
    The design of EUV lasers is already completely absurd. It's an awesome piece of engineering, but it's no easier to push the laser wavelength downwards than anything else.
    - Misdicorl 5y ago
      Does the lithography require the tight wavelength or other nice properties of lasers? I had thought they used filtered synchrotron output since a while ago. Basically everything about the process is absurd, not sure why pushing on the light source is less feasible then any of the other knobs
      - lazide 5y ago

k0stas 5y ago

It already has been a problem in terms of gate leakage, although largely mitigated by material improvements. Gate leakage is the phenomenon of quantum tunneling through the gate dielectric barrier and started appearing as gate dielectrics became thinner and thinner. Gate leakage was mitigated by moving to higher k dielectrics (from silicon dioxide, SiO2, to more exotic materials that include other elements such as Hafnium). Higher k dielectrics allow for the same capacitance per unit area and channel control with a thicker physical gate compared to plain SiO2, reducing gate leakage. This technology change came along with metal gates (which used to be polysilicon) and were a combined advance that Intel incorporated a few years before before TSMC, IIRC circa 2008. This is a circuit designer's perspective. Someone who actually understands device physics and material properties can chime in to correct me.

deleted 5y ago
[deleted]
baybal2 5y ago
Your nickname rings familiar. Ex-Xilinx by any chance?
istarial 5y ago
Do you have any books that you recommend on this topic? would love to get my hands dirty to the degree that i can with this

hajile 5y ago

From a few years ago until we perfect the QFET and can put it to use.