Both NICs and SSDs are connected to the CPU via PCIe: all SSD and NIC traffic already go through PCIe before they hit main memory today. PCIe 4.0 x16 is 64GB/s

Both NICs and SSDs are connected to the CPU via PCIe: all SSD and NIC traffic already go through PCIe before they hit main memory today. PCIe 4.0 x16 is 64GB/s, and there are 8 groups of x16 lanes in a 128 lane EPYC, for a total of 512GB/s or 4Tb/s, more than double the max fabric bandwidth of 200GB/s. Lets take the original diagram from the video: CPU ↑ ↓ Storage → Memory → NIC He was able to use NIC-kTLS offloading to simplify it to this: Storage → Memory → NIC Now lets add a bit more detail to the second diagram, expanding it to include PCIe: Memory ↑ ↓ Storage → PCIe → NIC This third diagram is the same as the diagram above it, except it explicitly describes how data gets from storage to memory and from memory to NIC. So the story for a request is something like: 1. request comes in for a file, loop { 2. CPU requests chunks of data, 3. data is delivered to memory via PCIe and signals CPU to handle it, 4. CPU tells NIC to send data from memory, 5. NIC requests data from memory via PCIe, sends it out on port } If you squint this looks kinda like the first diagram where there were extra unnecessary data transfers going up through the CPU, except now they're going up through main memory. My proposal is to skip main memory and go straight from storage to NIC as in: Storage → PCIe → NIC The story for serving a request would now be: 1. request comes in for a file, 2. CPU tells NIC: "ok get it from SSD 13", 3. NIC requests data from SSD via PCIe, sends it out on port, 4. cpu & main memory: crickets