3 ms·

I can not find anything to back up this claim. How else is AMD linking the multiple dies/sockets together?

• monocasa 5y ago
  The DDR phys are on the I/O die, so all of the core complexes have the same length path to DRAM. Multi socket is still NUMA, but that's true of Intel as well.
  • dragontamer 5y ago
    > The DDR phys are on the I/O die, so all of the core complexes have the same length path to DRAM. The I/O die has 4 quadrants. The 2 chips in the 1st quadrant access the 1st quadrant's 2-memory channels slightly faster than the 4th quadrant. > Multi socket is still NUMA, but that's true of Intel as well. Intel has 6-memory controllers split into pairs of 3 IIRC (I'm going off of my memory here). The "left" 3 memory channels access the "left 9 cores" a bit faster than the "right 9 cores" in an 18-core Intel Skylake-X chip. -------- Both AMD and Intel have non-uniform latency/bandwidth even within the chips that they make.
    • monocasa 5y ago
      There's a few cycles difference based on how the on chip network works, but variability in the number of off chip links between you and memory is what dominates the design. And in the context of what the parent said (but has since edited out), was what was being discussed.