Like I wrote, the Nios II is old. There’s barely any development going on. The compiler has a few bug fixes here and there. The libraries are all in C, CPU agn

Like I wrote, the Nios II is old. There’s barely any development going on. The compiler has a few bug fixes here and there. The libraries are all in C, CPU agnostic, and primarily there to support various Intel Platform Designer modules (you can easily verify that by looking at the BSP). None of that goes away when switching to RISC-V. I have no idea what you mean with “newer hardware interfaces”, especially in the context of reducing cost: when using RISC-V, you’ll have these newer hardware interfaces (whatever you mean by it) just the same. It’s not about how much money it costs to maintain the Nios infrastructure, its about how much they’ll save by adding(!) an extra CPU to support. Somewhat aside: most FPGA IP development of Intel happens in Malesia, so don’t assume US salaries… But if you estimate it at $10M-$50M, shall we agree that writing “billions” was more than a bit over the top? Intel will save a tiny bit on not having to maintain a custom GNU toolchain. That’s about it.