There's inherent complexity in the x86 instruction decoder, but after decoding, modern x86 CPUs don't particularly resemble legacy x86 CPUs internally. The nati

There's inherent complexity in the x86 instruction decoder, but after decoding, modern x86 CPUs don't particularly resemble legacy x86 CPUs internally. The native machine code is all proprietary "micro ops". A lot of the performance gains over the last couple decades haven't come from machine code changes, but rather from various forms of pipelining and superscaling. Rather than run one instruction at a time, CPUs run hundreds of instructions at a time. The complexity of doing that is that many instructions often depend on the result of instructions immediately before them, and so the CPU needs a lot of shortcut paths internally to keep from stalling out. You could get to Ghz speeds with a custom ASIC, and you could use base RISC-V as a modern, not crufty ISA. It still won't be anywhere near as fast as a high end x86 or ARM CPU, though, unless it's similarly pipelined and superscaled.