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> They said "5 stage", which sounds to me like no out-of-order fancy stuff of the sort we've been used to. There's a lot of processors out there. The vast, va
by monocasa 5y ago
> They said "5 stage", which sounds to me like no out-of-order fancy stuff of the sort we've been used to.
There's a lot of processors out there. The vast, vast majority being shipped are in order and a handful of stages.
> Well, I wrote a little 5 stage CPU FPGA program once (In Haskell compiled to Verilog :), but that's another story). It wasn't very hard.
> I haven't made a production IC, but I'm told that's much harder. I would be awesome if Intel made a RISC-V chip, even a slow one just good for arduino-type toys, but that's not what happened here.
The FPGA vendor provided soft cores have about the same amount of engineering rigor as a hard core. They have enough customers for the designs to have enough reach to have the same financial implications for bugs.
- gricardo99 5y agoThe FPGA vendor provided soft cores have about the same amount of engineering rigor as a hard core. I'm not sure what you mean by engineering rigor, but there is indeed plenty of engineering to get from a soft core to a hard core, let alone a fabricated, working chip: synthesis, layout, place and route, timing closure, pads, PLL/DLL, clock tree insertion, BIST, thermal, packaging, etc...
- monocasa 5y agoHigh end soft cores do most of that. Particularly when you consider that most of what isn't automated these days is equally applicable to soft cores that aren't just Verilog or VHDl. Floor planning FPGA cores these days can be nutty compared to the recent past (far past interestingly enough was similar before you had higher level tools). And the fact that stuff like packaging, DLLs/PLLs are equally applicable to hard cores. That's outside of what they care about on nearly every core design I've seen (albeit I'm only in my mid 30s).