5 ms·

This is out of my realm, isn't it at least a little relevant to vet a (logical) design with an fpga before doing the full process? Or are those worlds things wo

This is out of my realm, isn't it at least a little relevant to vet a (logical) design with an fpga before doing the full process? Or are those worlds things worlds apart?

duskwuff 5y ago
The FPGA was the final target for this design. It isn't intended to go anywhere else -- its predecessor, Nios II, was also FPGA-only.
Unklejoe 5y ago
Little soft core CPUs like this are often incorporated into larger FPGA designs to handle sub-tasks that would otherwise be annoying to implement with pure logic. Think something like a simple CLI console to configure low level board functionality, etc.
Ericson2314 5y ago
You could make a physical chip out of this, but there are lot of O(1) costs that mean I am not just going to download Quartus, call up my local fab, and get me a toy CPU from this for fun.
JoachimS 5y ago
In general yes. ASIC designs are prototyped using FPGAs. You often can't run at full clock speed. But can do orders more test cycles than in a simulator. But FPGAs are also used as final target technology. When volume is too low, time to market too tight, where flexibility is important, FPGAs are used. Building an ASIC takes 12-15-24 months (depending on design complexity, target process), and a respin (due to an error) of parts of the design adds months before the product can be released. Base stations for 3G/LTE/5G is a good example. They used to be built with a combination of ASICs and DSPs. But this took too long to develop, and was to rigid to handle upgrades (soft upgrade from 3G to LTE was/is a great selling point). Using FPGAs reduced development time, and provided generational upgrade in a much better way. Don't replace boards, just SW and FPGA bitstreams.
JoachimS 5y ago
If you want to see some FPGA emulator monsters, look at Cadence Palladium, or Mentor/Siemens Veloche. https://www.cadence.com/en_US/home/tools/system-design-and-verification/emulation-and-prototyping.html https://www.cadence.com/en_US/home/tools/system-design-and-v... https://eda.sw.siemens.com/en-US/ic/precision/ https://eda.sw.siemens.com/en-US/ic/precision/ They contain hundreds up to many thousands of FPGAs. Using support dev tools, you can take a large ASIC design and partition it over these FPGAs. We once used four interconnected machines like these to emulate a large superscalar, OOO CPU design. It took a few days, but could go from release of reset to loaded OS. Something impossible with a SW simulation. Fun times.

This is out of my realm, isn't it at least a little relevant to vet a (logical) design with an fpga before doing the full process? Or are those worlds things worlds apart?

duskwuff 5y ago

The FPGA was the final target for this design. It isn't intended to go anywhere else -- its predecessor, Nios II, was also FPGA-only.

Unklejoe 5y ago

Little soft core CPUs like this are often incorporated into larger FPGA designs to handle sub-tasks that would otherwise be annoying to implement with pure logic. Think something like a simple CLI console to configure low level board functionality, etc.

Ericson2314 5y ago

You could make a physical chip out of this, but there are lot of O(1) costs that mean I am not just going to download Quartus, call up my local fab, and get me a toy CPU from this for fun.

JoachimS 5y ago

In general yes. ASIC designs are prototyped using FPGAs. You often can't run at full clock speed. But can do orders more test cycles than in a simulator. But FPGAs are also used as final target technology. When volume is too low, time to market too tight, where flexibility is important, FPGAs are used. Building an ASIC takes 12-15-24 months (depending on design complexity, target process), and a respin (due to an error) of parts of the design adds months before the product can be released. Base stations for 3G/LTE/5G is a good example. They used to be built with a combination of ASICs and DSPs. But this took too long to develop, and was to rigid to handle upgrades (soft upgrade from 3G to LTE was/is a great selling point). Using FPGAs reduced development time, and provided generational upgrade in a much better way. Don't replace boards, just SW and FPGA bitstreams.

JoachimS 5y ago

If you want to see some FPGA emulator monsters, look at Cadence Palladium, or Mentor/Siemens Veloche. https://www.cadence.com/en_US/home/tools/system-design-and-verification/emulation-and-prototyping.html https://www.cadence.com/en_US/home/tools/system-design-and-v... https://eda.sw.siemens.com/en-US/ic/precision/ https://eda.sw.siemens.com/en-US/ic/precision/ They contain hundreds up to many thousands of FPGAs. Using support dev tools, you can take a large ASIC design and partition it over these FPGAs. We once used four interconnected machines like these to emulate a large superscalar, OOO CPU design. It took a few days, but could go from release of reset to loaded OS. Something impossible with a SW simulation. Fun times.