Back in the 1990s I did the UC Berkeley computer hardware qualifying exam, which required building an entire pipelined RISC processor bottom-up out of nothing b

Back in the 1990s I did the UC Berkeley computer hardware qualifying exam, which required building an entire pipelined RISC processor bottom-up out of nothing but NAND gates. We had three hours. Of course you build latches and D-flops out of NAND gates with feedback, and we could assume an external source for the clock. It was fun but I wouldn't want to do it again.