If it’s because of having to map the BARs as device memory, then it’s a problem that will be taken care of. That said, the details of the right approach to work

If it’s because of having to map the BARs as device memory, then it’s a problem that will be taken care of. That said, the details of the right approach to work around this isn’t quite ironed out yet. On Apple M1, trying to map the BARs as normal memory directly causes an SError. As a reminder, the Arm Base System Architecture spec mandates that PCIe BARs must be mappable as normal non-cacheable memory.