> These are defined in a way that they cannot be interrupted mid-instruction... Usually. Cortex-M3 and M4 cores allow LDM/STM to be interrupted by default, and

> These are defined in a way that they cannot be interrupted mid-instruction... Usually. Cortex-M3 and M4 cores allow LDM/STM to be interrupted by default, and offer a flag to disable that (SCB->ACTLR.DISMCYCINT). https://developer.arm.com/documentation/ddi0439/b/System-Control/Register-descriptions/Auxiliary-Control-Register--ACTLR https://developer.arm.com/documentation/ddi0439/b/System-Con...