3 ms·

Note that in ARM-based controllers, LDM/STM also have a non-negligible impact on interrupt latency. These are defined in a way that they cannot be interrupted

Note that in ARM-based controllers, LDM/STM also have a non-negligible impact on interrupt latency. These are defined in a way that they cannot be interrupted mid-instruction, so worst-case interrupt latency is higher that would be expected with a RISC CPU (especially if LDM/STM happen to run on a somewhat slower memory region) AFAICS x86 "rep" prefixed instructions are defined so that they can in fact be interrupted without problems. The remaining count is kept in (e)cx, so just doing an iret into "rep stosb" etc. will continue its operation. I think VIA's hash/aes instruction set extension also made use of the "rep" prefix and kept all encryption/hash state in the x86 register set, so that they could in fact hash large memory regions on a single opcode without hampering interrupts.

duskwuff 5y ago
> These are defined in a way that they cannot be interrupted mid-instruction... Usually. Cortex-M3 and M4 cores allow LDM/STM to be interrupted by default, and offer a flag to disable that (SCB->ACTLR.DISMCYCINT). https://developer.arm.com/documentation/ddi0439/b/System-Control/Register-descriptions/Auxiliary-Control-Register--ACTLR https://developer.arm.com/documentation/ddi0439/b/System-Con...
- dvdkhlng 5y ago
  Yes, looks like they added a few bits to the PSR register to capture the internal state of LDM/STM . Like a small version of x86's CS register.
userbinator 5y ago
AFAICS x86 "rep" prefixed instructions are defined so that they can in fact be interrupted without problems. The remaining count is kept in (e)cx, so just doing an iret into "rep stosb" etc. will continue its operation. The 8086/8088 have a bug (one of very few!) where segment override prefixes were lost after an interrupted string instruction: https://www.pcjs.org/documents/manuals/intel/8086/ https://www.pcjs.org/documents/manuals/intel/8086/ I believe it was fixed in later versions.

duskwuff 5y ago

> These are defined in a way that they cannot be interrupted mid-instruction... Usually. Cortex-M3 and M4 cores allow LDM/STM to be interrupted by default, and offer a flag to disable that (SCB->ACTLR.DISMCYCINT). https://developer.arm.com/documentation/ddi0439/b/System-Control/Register-descriptions/Auxiliary-Control-Register--ACTLR https://developer.arm.com/documentation/ddi0439/b/System-Con...

dvdkhlng 5y ago
Yes, looks like they added a few bits to the PSR register to capture the internal state of LDM/STM . Like a small version of x86's CS register.

userbinator 5y ago

AFAICS x86 "rep" prefixed instructions are defined so that they can in fact be interrupted without problems. The remaining count is kept in (e)cx, so just doing an iret into "rep stosb" etc. will continue its operation. The 8086/8088 have a bug (one of very few!) where segment override prefixes were lost after an interrupted string instruction: https://www.pcjs.org/documents/manuals/intel/8086/ https://www.pcjs.org/documents/manuals/intel/8086/ I believe it was fixed in later versions.