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It's strange that such features seem to not be standard in CPUs. I wonder why? Copy-based APIs are not ideal but they seem to be hard to avoid. In those ARM c
by colonwqbang 5y ago
It's strange that such features seem to not be standard in CPUs. I wonder why? Copy-based APIs are not ideal but they seem to be hard to avoid.
In those ARM cores I've programmed, the core has a few extra DMA channels which can be used for such things. However, using them from userspace has always seemed a bit of a hassle.
- hannob 5y agoI haven't done assembler for a long time, but if my memory serves me well on x86 there's the rep movsb commands that will do effectively a memcpy-like operation.
- hyperman1 5y agoCorrect. There is the whole rep family doing all kinds of fun stuff. You can add the rep/repnz/repz prefixes to at least: movs[b|w|d]: move data in bytes/words/doublewords aka memcpy stos[b|w|d]: put a value in bytes/words/dwords aka memset cmps[b|w|d]: compare values aka memcmp scas[b|w|d]: scan for a value aka memchr ins[b|w|maybe d]: read from IO port outs[b|w|maybe d]: write to IO port. lods[b|w|d] : read from memory was probably not meant to be combined with rep as it would just throw everything but the last byte away. I once saw a rep lodsb to do repeated reads from EGA video ram. The video card saw which bytes were touched and did something to them based on plane mask. This way touching 1 bit changed the color of a whole 4 bit pixel, speeding up things with a factor 4. Then one day, someone found that rep movs was not the fastest way to copy data on an x86 and they all went out of vogue. I think rep stos recently came back as fastest memset, as it had a very specific CPU optimization applied. Update: See https://stackoverflow.com/questions/33480999/how-can-the-rep-stosb-instruction-execute-faster-than-the-equivalent-loop https://stackoverflow.com/questions/33480999/how-can-the-rep...
- vardump 5y ago"Copy-based APIs are not ideal but they seem to be hard to avoid." If everything resides in CPU L1 cache, it hardly matters at all. Other than L1 cache pressure, of course. Other example is copying DMA transferred data followed by immediately consuming said data. Also in this case, the copy often effectively just brings the data to the CPU cache and the consuming code reads from cache. Of course it does increase overall memory write bandwidth use when the cache line(s) are eventually evicted, but total performance degradation can be pretty minimal for anything that fits in L1.