4 ms·
Instructions like this need to be interruptible since they take longer than standard instructions. I assume the ARM designers have thought about this?
by cjensen 5y ago
Instructions like this need to be interruptible since they take longer than standard instructions. I assume the ARM designers have thought about this?
- addaon 5y agoThe old ARM<=7 load multiple / store multiple instructions were interruptible on most implementations. My recollection is that some implementations checkpointed and resumed, but at least the smaller cores tended to do a full-restart (so no guarantee of forward progress when approaching livelock). I'd expect the same here, with perhaps more designs leaning towards checkpointing.
- baybal2 5y agoIt's well known in the ARM world, and it's the reason we were complaining for years about impossibility of using DMA controller from userspace to do large memcpys. More importantly today, using DMA to do large memcpy for non-latency-sensitive tasks allows cores to sleep more often, and it's a godsend for I/O intensive stuff like modern Java apps on Android which are full of giant bitmaps.
- brandmeyer 5y agoARMv7-M squirrels away the progress of the ldm/stm in the program status register to avoid restarting it completely.
- brandmeyer 5y agoARM has been managing interruptible instructions with partial execution state for a long time. In ARM assembly syntax, the exclamation point in an addressing mode indicates writeback. Its difficult to be certain without seeing the architecture reference manual, but it would be consistent for instruction to be writing back all three of the source pointer, destination pointer, and length registers. A memcpy is interruptible without replaying the entire instruction (say, because it hit a page that needed to be faulted-in by the operating system) if it wrote back a consistent view of all three registers prior to transferring control to an interrupt handler.