3 ms·
Well, I have a doubt that simply increasing bus size to 64 bits you can get working bitstream for FPGAs, even for top notch ones. Something tells me that synthe
by ruslan 5y ago
Well, I have a doubt that simply increasing bus size to 64 bits you can get working bitstream for FPGAs, even for top notch ones. Something tells me that synthesising/placing/routing such soft-core will face timing and resource limitations.
Studying recent ARM based SoCs I usually find that they often use reduced AXI4 buses to 48 or even less bits, making all internal I/O transactions block-wise.
- brucehoult 5y agoOf course you can do it and it will work. A "standard" (e.g. 5 stage pipe in-order) 64 bit RISC-V core takes a very small proportion of even a fairly small FPGA such as an Arty 100T. You can even do multiple cores. 128 bit would fit no problem at all. You'd probably have slightly lower Fmax but there's no question about working and if you actually need 128 bit arithmetic then it will be faster than using multiple instructions on a 64 bit CPU (e.g. 4 instructions for a 128 bit add).