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Whatever system you are talking about doesn't exist, not in the way you described at least.
by SubjectToChange 5y ago
Whatever system you are talking about doesn't exist, not in the way you described at least.
- jandrewrogers 5y agoThe prototype for architectures with these properties were the Tera MTA supercomputers. These were evolved by Cray but a few other companies (including Intel) experimented with and produced their own variants of the concept. It was a great model once you grokked it. The general idea is that every memory address has several semantic bits that annotate the contents on load and store. Each core has multiple independent hardware threads (128 in the case of MTA) which adapt their scheduling to those annotations on a clock cycle by clock cycle basis. You can design massively multithreaded code for these platforms with almost perfect scalability that would have catastrophically high contention and overhead anywhere else, which was the point. There are quirks to designing software for these systems, but they don’t involve safety.
- SubjectToChange 5y agoBarrel processors still need to be programmed with parallelism and cache behavior in mind. And if normal imperative code can't be reused with minimal modification, than such a device holds little appeal over GPUs (as Intel found out with Xeon Phi). "There are quirks to designing software for these systems, but they don’t involve safety." Parallel programming is intrinsically racey. Even if hardware could enforce safety like you're saying (which it can't, even in a single thread) it would imply a sequentially consistent memory model, i.e. the antithesis of any parallel machine.