The OMI issue is probably solvable with an open controller. Not a trivial undertaking but OMI, at least, is documented. The on-chip PPE I/O controller is a big

The OMI issue is probably solvable with an open controller. Not a trivial undertaking but OMI, at least, is documented. The on-chip PPE I/O controller is a bigger problem. I suspect, but don't know, that it's the PCIe interface. If so, I can't think of an easy way of getting around it.