Minor correction to the article. It mentions that each PCIe lane has two wires. One for inbound and one for outbound. I think this should really read that each

Minor correction to the article. It mentions that each PCIe lane has two wires. One for inbound and one for outbound. I think this should really read that each lane has two differential pairs (interestingly the diagram shows twisted pairs). One for inbound, one for outbound. Which sums to four wires (or traces) in total for each lane. I’m also a little confused about the whole > A lane is composed of 2 wires: one for inbound communications and one, which has double the traffic bandwidth, for outbound. Not really sure what the author is trying to say. But the ideas that outbound has double the bandwidth doesn’t really make much sense, as outbound is different depending on perspective as a device. So I read this statement as saying that each device transmits at twice the speed the receiving device can receive data. Which is clearly non-sensical.