They're standard cell logic designs (so ASICs, but what you get from letting the tooling just create a chip from the HDL more or less) that haven't had a lot of

They're standard cell logic designs (so ASICs, but what you get from letting the tooling just create a chip from the HDL more or less) that haven't had a lot of work put into power management compared to similar chips like nrf5x. They're not hard configured FPGAs. Which makes sense, as their original target was as a SDIO WIFI chip for a much larger, power hungry system, not a standalone device.